The MPEG standard is an international standard relating to an image compression. A dynamic image coding technique and a dynamic image decoding technique based on the MPEG standard are the techniques that are unavoidable in the recent multimedia environment. Thus, there have been developed many dynamic image coding apparatuses and dynamic image decoding apparatuses that employ the MPEG standard.
In the MPEG standard, three types of pictures are used for achieving high-efficiency coding. These three types are, intra-coded picture (hereinafter to be referred to as an I picture), a predictive-coded picture (hereinafter to be referred to as P picture), and a bidirectionally predictive-coded picture (hereinafter to be referred to as B picture).
The I picture is coded based on only the picture information of its own, that is, without using other picture information. As the I picture can be coded independent of other pictures, the I picture is used as an access point at the time of a random access. Therefore, other picture information is not necessary for decoding the I picture.
The P picture is coded by using a past I picture or a past P picture as a reference picture. Therefore, the information of a past I picture is necessary for decoding the P picture.
The B picture is coded by using past and future I pictures or past and future P pictures as reference pictures. Therefore, the information of past and future I pictures or P pictures are necessary for decoding the B picture.
A hierarchical coding system is employed in the MPEG standard. In other words, a video sequence consists of six hierarchical layers in total. They are a sequence layer, a group-of-picture layer (hereinafter to be referred to as GOP layer), a picture layer, a slice layer, a macro block layer (hereinafter to be referred to as MB layer), and a block layer, in the order starting from a highest-order layer. The four high-order layers starting from the sequence layer to the slice layer are added with a start code respectively to show the start of each layer.
Following each start code, parameters are coded for each layer. For example, the sequence layer has a sequence header code (SHC) at the beginning, and then has, as parameters, a horizontal size value, a vertical size value, aspect ratio information, etc. which are superimposed in this order.
The table in FIG. 1 shows a part of parameters for each layer of the MPEG standard. In the case of the sequence layer, the horizontal size value and the vertical size value are parameters that express the sizes of an image in the horizontal direction and the vertical direction respectively. In other words, they are the parameters that express numbers of pixels in the horizontal direction and the vertical direction respectively. The aspect ratio information is a parameter that expresses the aspect ratio of the pixels. In addition to these parameters, the sequence layer also has other parameters, such as a display horizontal size and display vertical size that express the display sizes of a decoded image in the horizontal direction and in the vertical direction respectively.
The GOP layer has two parameters. They are, a closed group of picture (closed gop) that expresses that it is possible to display a B picture at the head of the GOP, and a broken link that expresses that it is not possible to display a B picture at the head of the GOP.
The picture layer has four parameters. First two parameters are a top field first that expresses that a display is made starting from a picture of a first field, and a repeat first field that expresses that a picture in the first field is displayed repeatedly. Other two parameters are a frame center horizontal offset and a frame center vertical offset that are pan-scan parameters.
A conventional MPEG video decoder generally stores these parameters of each layer into a register inside the decoder, and refers to these parameters at the time of making a display. The structure of the conventional MPEG video decoder will be explained below.
FIG. 2 is a block diagram that shows a structure of the conventional MPEG video decoder. This MPEG video decoder consists of a buffer memory 11, an image decoding section 12, a frame buffer 13, a decode control section 14, and a display control section 15. The buffer memory 11 stores an MPEG bit stream that has been transmitted from a transmission path or a storing medium. The image decoding section 12 decodes a bit stream that has been transmitted from the buffer memory 11, and generates a picture.
The frame buffer 13 stores a picture generated by the image decoding section 12. The frame buffer 13 has a capacity for storing three pictures. The frame buffer 13 is divided into three areas which respectively store one picture. Each area is called a bank. In other words, the frame buffer 13 has three banks, a first bank 13a, a second bank 13b and a third bank 13c. Each of the banks 13a, 13b and 13c has its own address (i.e., bank address).
The decode control section 14 incorporates a vertical synchronization signal generator 16 that generates a vertical synchronization signal (V-Sync) 21. The decode control section 14 issues a slice layer decode starting instruction 22 to the image decoding section 12 and the display control section 15. The slice layer decode starting instruction 22 is synchronous with the vertical synchronization signal (V-Sync) 21. The cycle of issuing the slice layer decode starting instruction 22 is basically once per every two field time, that is, once per one frame time. This cycle is for matching the decoding speed with the display speed, as the display speed is at the rate of displaying one picture during one frame time. When the capacity of the buffer memory 11 has satisfied a predetermined condition at the time of a cold starting, the decode control section 14 issues an initial decode starting instruction 23. The timing of issuing the initial decode starting instruction 23 is not related to the vertical synchronization signal (V-Sync) 21.
The display control section 15 incorporates registers for storing parameters 24 of each layer decoded by the image decoding section 12 and a bank address 25. These registers include a reorder register 15a, a current register 15b, a field delay register 15c, and a display register 15d. The bank address 25 is the address of the bank in the frame buffer 13 in which a decoded picture is stored.
The display control section 15 receives a sequence layer decode completion notice 26 and a GOP layer decode completion notice 27 from the image decoding section 12. The sequence layer decode completion notice 26 is issued at a point of time when the decoding of the parameters of the sequence layer has been finished. The GOP decode completion notice 27 is issued at a point of time when the decoding of the parameters of the GOP layer has been finished.
The display control section 15 is supplied with the vertical synchronization signal (V-Sync) 21 from the vertical synchronization signal generator 16. The display control section 15 outputs a display starting instruction 28 to the frame buffer 13 at a timing synchronous with the vertical synchronization signal (V-Sync) 21. Based on this display starting instruction 28, the frame buffer 13 transfers a predetermined picture to a display unit not shown, and the display unit displays the image.
As explained above, the MPEG video decoder starts the decoding of a bit stream for one picture at a timing synchronous with the vertical synchronization signal (V-Sync) 21, and transfers the picture to the display unit at a timing synchronous with the vertical synchronization signal (V-Sync) 21. Thus, the image displayed by the display unit is updated at the timing synchronous with the vertical synchronization signal (V-Sync) 21, and the display unit displays a dynamic image.
FIG. 3 is a diagram that shows a structure of the registers within the display control section 15. The display control section 15 is provided with a sequence layer parameter register 15e, a GOP layer parameter register 15f, and picture layer parameter registers 15g. When the sequence layer parameter register 15e has received the sequence layer decode completion notice 26, the sequence layer parameter register 15e stores the parameters of the horizontal size value and the vertical size value of the sequence layer out of the parameters 24 of each layer.
When the GOP layer parameter register 15f has received the GOP layer decode completion notice 27, the GOP layer parameter register 15f stores the parameters of the closed group of picture and the broken link of the GOP layer out of the parameters 24 of each layer. The picture layer parameter registers 15g include the reorder register 15a, the current register 15b, the field delay register 15c, and the display register 15d described above.
Parameters that are stored in the picture layer parameter register group 15g include a temporal reference, a picture coding type, and a picture structure of the picture layer respectively, out of the parameters 24 of each layer. The picture layer parameter register group 15g stores the bank address 25.
The reason why there are four registers 15a, 15b, 15c and 15d for storing the picture layer display parameters and the bank address 25 is that, according to the MPEG standard, it is necessary to reorder the I picture, the P picture and the B picture. In other words, as mentioned above for decoding the B picture, the past and future pictures are referred. Therefore, it is necessary to reorder the pictures in order to process the future picture first.
The reorder register 15a stores the picture layer parameters and the bank address 25 of the I picture and the P picture respectively. The I picture and the P picture are not displayed straight when the decoding of these pictures has been completed. It is necessary to reorder these pictures with the B picture. Therefore, the parameters and the bank address 25 of the I picture and the P picture respectively are once saved in the reorder register 15a. 
The current register 15b stores the picture layer display parameter of the picture to be displayed and the bank address 25. As the B picture is displayed immediately after the completion of the decoding, the parameters and the bank address 25 of the B picture are not stored in the reorder register 15a but are stored directly in the current register 15b. 
The field delay register 15c delays the bank address 25 transferred from the current register 15b by one field time in order to set the decoding time to one frame time, and then transfers the delayed result to the next display register 15d. If it is assumed that the field delay register 15c is not present, then the field slot of the display timing becomes the field slot immediately after the field slot of the decoding timing. As a result, it is not possible to perform the display at the right timing. The data that is stored in the field delay register 15c is only the bank address 25.
The display register 15d stores the bank address 25 of the picture currently being displayed. In other words, the display control section 15 issues the display starting instruction 28 so that a picture indicated by the bank address 25 stored in the display register 15d is displayed. The data stored in the display register 15d is only the bank address 25, and the display register 15d takes in the content of the display register 15c as it is. The display control section 15 executes the display of the picture by comprehensively analyzing the display parameter of the picture layer stored in this register and the parameters of the sequence layer and the parameters of the GOP layer.
These four registers 15a to 15d have a shift register structure as shown in FIG. 3. The shift pulse of the reorder register 15a and the current register 15b is the slice layer decode starting instruction 22, and the shift pulse of the field delay register 15c and the display register 15d is the vertical synchronization signal (V-Sync) 21. The bank address 25 shifts to all the registers from the reorder register 15a to the display register 15d, but the display parameter of the picture layer shifts only up to the current register 15b. 
The operation of the MPEG video decoder having the above-described conventional structure will be explained next. The time chart shown in FIG. 4 explains the operation of the conventional MPEG video decoder. In the example shown in FIG. 4, it is assumed that a bit stream is input in the order of an I picture I2, a B picture B0, a B picture B1, a P picture P5, a B picture B3, a B picture B4, and so on, and that the pictures are displayed in the order of the picture B0, the picture B1 the picture I2, the picture B3, and so on.
The MPEG bit stream obtained through the transmission path or the storing medium is first stored in the buffer memory 11. When a certain amount of data (for example, data for one picture) has accumulated in the buffer memory 11, the decode control section 14 issues the initial decode starting instruction 23 (at time t0). When the image decoding section 12 has received the initial decode starting instruction 23, the image decoding section 12 starts the decoding of the bit stream, and first carries out the decoding of a first picture. When the image decoding section 12 has finished the decoding of all the parameters of the sequence layer, the image decoding section 12 issues the sequence layer decode completion notice 26. When the display control section 15 has received the sequence layer decode completion notice 26, the display control section 15 stores the parameters of the sequence layer in the sequence layer parameter register 15e (at time t1).
Next, the image decoding section 12 carries out the decoding of the parameters of the GOP layer. When the image decoding section 12 has finished the decoding of the parameters of the GOP layer, the image decoding section 12 issues the GOP layer decode completion notice 27. When the display control section 15 has received the GOP layer decode completion notice 27, the display control section 15 stores the parameters of the GOP layer in the GOP layer parameter register 15f (at time t2). Further, the image decoding section 12 decodes the parameters of the picture layer of the picture I2 and reads the decoded parameters, and then halts temporarily (at time t3).
Thereafter, in synchronism with the pulse of the vertical synchronization signal (V-Sync), the decode control section 14 issues the slice layer decode starting instruction 22 (at time t4). When the image decoding section 12 has received the slice layer decode starting instruction 22, the image decoding section 12 decodes the slice layer and the MB (macro block) layer of the picture I2. When the decoding of the MB layer has been completed, the image decoding section 12 decodes the picture layer of the next picture B0. When the decoding of the picture layer of the picture B0 has been completed, the image decoding section 12 halts temporarily again (at time t5).
In the mean time, at time t4, the display control section 15 receives the picture parameter of the picture I2 from the image decoding section 12, and stores the picture parameter in the reorder register 15a. In this case, the reorder register 15a stores the parameters of the picture I2 at a timing synchronous with the slice layer decode starting instruction 22 using the slice layer decode starting instruction 22 as a latch pulse.
At time t6, the decode control section 14 issues the slice layer decode starting instruction 22 again in synchronism with the vertical synchronization signal (V-Sync) 21. When the image decoding section 12 has received this slice layer decode starting instruction 22, the image decoding section 12 starts the decoding of the slice layer and the MB layer of the picture B0. At the same time, the image decoding section 12 stores the picture parameter of the picture B0 into the current register 15b. 
The picture parameter of the picture B0 is shifted to the field delay register 15c in synchronism with the vertical synchronization signal (V-Sync) 21, and is further stored in the display register 15d in synchronism with the next vertical synchronization signal (V-Sync) 21 (at time t7). Thus, the data of the pictures to be displayed have been arranged, and the pictures are ready for display. Then, the display control section 15 comprehensively analyzes the display layer parameters, the sequence layer parameters, and the GOP layer parameters, and determines how to display this B0.
Assume, for example, that the horizontal size value is “720”, the vertical size value is “480”, the value of the closed group of picture is “1”, the value of the broken link is “0 (zero)”, the value of the top field first is “1”, the value of the repeat first field is “0 (zero)”, and the values of the frame center horizontal offset and the frame center vertical offset are both “0 (zero)”. In this case, the display control section 15 makes a decision that as the picture B0 is effective, this picture is displayed, and that the display is carried out in an ordinary manner instead of carrying out a pan-scan display in the pixel size of “720×480”.
Thereafter, the display control section 15 issues the display starting instruction 28 to the frame buffer 13, and makes the picture displayed in the region shown by the horizontal size value and the vertical size value.
Thereafter, the image decoding section 12 carries out the decoding sequentially in a similar manner. For making a display of the B picture, the display control section 15 progresses the display by referring to the display parameter of the picture layer stored in the current register 15b and the display parameters of the sequence layer and the GOP layer. Further, for making a display of the I picture or the P picture, the display control section 15 progresses the display by referring to the display parameter of the picture layer stored in the display register 15d and the display parameters of the sequence layer and the GOP layer.
In the television image according to the NTSC (National Television System Committee) system, one frame is divided into two fields (a top field and a bottom field). Therefore, in FIG. 4 (as well as in FIG. 5, FIG. 7 and FIG. 8), each picture is shown by being divided into the top field (a field indicated by “T” in the drawing) and the bottom field (a field indicated by “B” in the drawing).
However, according to the above-described conventional MPEG video decoder, when a bit stream has only one picture in one sequence and also when the bit stream having a plurality of these sequences connected together (generally called a slide show) is to be decoded and displayed, the following two problems arise. These problems will be explained next.
The time chart shown in FIG. 5 explains the operation in a slide show of the conventional MPEG video decoder. A case where three sequences are connected together, each sequence having one picture, will be explained as an example. The three sequences will be called SEQ1, SEQ2 and SEQ3. In this case, as one sequence has one picture, a display parameter of the sequence layer exists in each of the three pictures.
Assume that the first sequence SQ1 has a value of “720” for the horizontal size value and a value of “480” for the vertical size value, the second sequence SQ2 has a value of “360” for the horizontal size value and a value of “240” for the vertical size value, and the third sequence SQ3 has a value of “360” for the horizontal size value and a value of “480” for the vertical size value.
In this case, as shown in FIG. 5, the operation from time t0 to t3 is the same as the operation of the normal display shown in FIG. 4. However, as shown in FIG. 5, the first sequence SEQ1 changes to the second sequence SEQ2 at time t4. Therefore, the sequence layer display parameter is updated from the parameter of the first sequence SEQ1 to the parameter of the second sequence SEQ2. In other words, the horizontal size of the image is updated from 720 pixels to 360 pixels, and the vertical size of the image is updated from 480 pixels to 240 pixels. Further, the second sequence SEQ2 is updated to the third sequence SEQ3 at time t5. At this point of time, the display parameter of the second sequence SEQ2 is updated to the display parameter of the third sequence SEQ3. Therefore, the vertical size of the image is updated from 240 pixels to 480 pixels. As a result, the sizes of the image are changed to “360×480” pixels.
In the case of displaying the I2 picture of the first sequence SEQ1 at time t6, the picture must be displayed in the sizes of “720×480” in principle. However, as the display parameter has been updated to the parameter of the third sequence at time t6, the I2 picture of the first sequence SEQ1 is displayed by the pixel sizes of “360×480”. In other words, as the combination of the picture parameters and the sequence layers of the three sequences are not managed completely, the decoded images are not displayed correctly. Same thing can be said about the display parameter of the GOP layer though its explanation has been omitted. This is a first problem. This problem also occurs when a pause, a quick winding or a rewinding operation has been carried out for the MPEG bit stream that has been sent from the storing medium.
This problem occurs because only one register is provided for the sequence layer parameter register 15e and the GOP layer parameter register 15f respectively in the display control section 15. Therefore, only one set of the sequence parameters and the GOP parameters can be held in these registers 15e and 15f respectively. As a result, when different sequences continue like the slide show, the sequence parameters and the GOP parameters are overwritten and updated sequentially.
The second problem is that as there is no fourth sequence after the third sequence SEQ3, which is the last sequence of this slide show, the third sequence SEQ3 cannot be displayed. This is because when the slice layer decode starting instruction to the fourth sequence is not issued from the decode control section 14, the picture parameters of the third sequence SEQ3 stored in the reorder register 15a cannot be shifted to the current register 15b at time t6. When the picture parameters of the third sequence SEQ3 are not shifted to the current register 15b, the parameters are not shifted to the field delay register 15c and the display register 15d either. As a result, the third sequence SEQ3 is not displayed at all.
In order to decode and display the slide show by the MPEG video decoder having the above-described conventions structure, it is necessary to add in advance an additional sequence to the end of the last sequence, and to take a sufficiently long time between the sequences in order to avoid the overwriting of the parameters stored in the sequence layer parameter register 15e and the GOP layer parameter register 15f respectively. However, based on this arrangement, it is not possible to completely achieve the display of the slide show.